Display driver integrated circuit, display system, and method for driving display driver integrated circuit

ABSTRACT

A display system includes: a host processor for outputting a data load command and outputting compensated image data obtained by compensating for image data; a non-volatile memory for storing compensation data for image compensation; and a display module controlled by the host processor, wherein the display module includes: a display panel including a plurality of pixels, the display panel displaying an image, based on the compensated image data; and a display driver integrated chip (DDI) coupled to the host processor through a first interface, the DDI being coupled to the non-volatile memory through a second interface, the DDI including an interface packet converter for performing packet structure conversion on each of first data compatible with the first interface and second data compatible with the second interface.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119(a) to Koreanpatent application 10-2017-0144798 filed on Nov. 1, 2017 in the KoreanIntellectual Property Office, the entire disclosure of which isincorporated herein by reference.

BACKGROUND 1. Technical Field

Example embodiments of the present disclosure relates to an electronicdevice including a display system. More particularly, exampleembodiments of the present disclosure relate to a display driverintegrated circuit and a display system including the same.

2. Related Art

An electronic device having an image display function, such as acomputer, a tablet PC, a smart phone, or a wearable electronic device,includes a display system.

As the performance of a display, an image sensor, and the like, whichare included in an electronic device such as a mobile device, isimproved and their resolution increases, the amount of data transmissionto the display is rapidly increasing. Studies for serial interfaces suchas a mobile industry processor interface (MIPI) and a mobile displaydigital interface (MDDI) have been actively conducted to support imageshaving high resolution of nHD (n*360*640) or more.

Meanwhile, studies have also been actively conducted to compensate forimage data having high resolution. Currently, compensation driving forcompensating for image data is performed in a DDI (display driverintegrated chip, or display driver integrated circuit) of a displaysystem or in the pixels. In one example, the DDI includes a physicalcompensation block, such as a compensation logic circuit.

For these reasons, the number of physical lanes of an interface betweenchips or devices used in a display system such as a mobile device isincreasing, and many problems can result. For example, degradation ofsignal integrity due to interference between the chips or devices andelectromagnetic interference (EMI) can result. and the increased numberof lanes may lead to more complex arrangement of the chips for physicalconnection. In addition, the size and manufacturing cost of the DDI mayincrease in order to provide the compensation driving.

SUMMARY

Embodiments provide a display driver integrated chip (DDI) including aninterface packet converter for mediating communication between a firstinterface and a second interface.

Embodiments also provide a display system including the DDI.

Embodiments also provide a method for driving the DDI.

According to example embodiments, there is provided a display systemincluding: a host processor configured to output a data load command andoutput compensated image data obtained by compensating for image data; aflash memory configured to store compensation data for imagecompensation; and a display module controlled by the host processor,wherein the display module includes: a display panel including aplurality of pixels to display an image, based on the compensated imagedata; and a DDI coupled to the host processor through a first interface,the DDI being coupled to the flash memory through a second interface,the DDI including an interface packet converter configured to performpacket structure conversion on each of first data compatible with thefirst interface and second data compatible with the second interface.

The interface packet converter may include: a first converter configuredto rearrange a packet structure of the first data received through thefirst interface in a format compatible with the second interface; and asecond converter configured to rearrange a packet structure of thesecond data received through the second interface in a format compatiblewith the first interface.

The first data may correspond to the data load command for loading datastored in the flash memory, and the second data may correspond to thecompensation data read from the flash memory, based on the data loadcommand.

The first interface may correspond to a mobile industry processorinterface (MIPI), and the second interface may correspond to a serialperipheral interface (SPI).

The compensation data may include at least one of offsets for opticalcompensation and offsets for afterimage compensation.

The host processor may perform image data compensation on the imagedata, based on the compensation data, to generate the compensated imagedata, and provide the compensated image data to the display modulethrough the first interface.

The host processor may include an image data compensator configured toperform at least one of optical compensation and afterimage compensationon the image data, based on the compensation data.

The host processor may perform communication with the flash memory viaDDI.

According to example embodiments, there is provided a DDI including: afirst interface coupled to communication channels for communication withan external host processor; a second interface coupled to communicationchannels for communication with an external memory, the second interfacebeing different from the first interface; an interface packet converterconfigured to perform packet structure conversion on each of first datacompatible with the first interface and second data compatible with thesecond interface; and a timing controller configured to generate a datasignal for image display, a scan control signal, and a data controlsignal by receiving image data processed through the first interface.

The interface packet converter may include: a first converter configuredto rearrange a packet structure of the first data received through thefirst interface in a format compatible with the second interface; and asecond converter configured to rearrange a packet structure of thesecond data received through the second interface in a format compatiblewith the first interface.

The first data may correspond to a data load command for loading datastored in the memory, and the second data may correspond to data readfrom the memory, based on the data load command.

The interface packet converter may mediate data transmission between thefirst interface and the second interface.

The first interface may correspond to a MIPI, and the second interfacemay correspond to an SPI.

The first interface may conform with MIPI Alliance Specification forDisplay Serial Interface and MIPI Alliance Specification for D-PHY.

The second interface may correspond to a low-speed serial interface.

The display driver integrated circuit may further include a data driverconfigured to generate a data voltage in response to the data signal andthe data control signal.

The display driver integrated circuit may further include a scan driverconfigured to generate a scan signal in response to the scan controlsignal.

According to example embodiments, there is provided a method for drivinga DDI, the method including: receiving a data load command for imagecompensation, which is output from a host processor, through a firstinterface; converting a packet structure of the data load command to becompatible with a second interface; and transmitting the converted dataload command to an external non-volatile memory (NVM) through the secondinterface.

The method may further include: receiving compensation data loaded fromthe NVM through the second interface; converting a packet structure ofthe compensation data to be compatible with the first interface; andtransmitting the converted compensation data to the host processorthrough the first interface.

The first interface may correspond to a MIPI, and the second interfacemay correspond to an SPI.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein.

Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the exampleembodiments to those skilled in the art.

In the drawing figures, dimensions may be exaggerated for clarity ofillustration. It will be understood that when an element is referred toas being “between” two elements, it can be the only element between thetwo elements, or one or more intervening elements may also be present.Like reference numerals refer to like elements throughout.

FIG. 1 is a block diagram illustrating a display system according to anembodiment.

FIG. 2 is a diagram schematically illustrating an example of a displaydriver integrated chip (DDI) according to an embodiment.

FIG. 3 is a block diagram illustrating an example of an interface packetconverter included in the DDI of the display system of FIG. 1.

FIG. 4 is a block diagram illustrating an example of a configuration ofa first interface included in the DDI according to an embodiment.

FIGS. 5A to 5C are diagrams schematically illustrating examples of apacket structure according to the first interface of FIG. 4.

FIG. 6 is a diagram schematically illustrating an example of a packetstructure of a second interface included in the DDI.

FIG. 7A is a diagram schematically illustrating an example of driving ofthe DDI included in the display system of FIG. 1.

FIG. 7B is a diagram schematically illustrating another example of thedriving of the DDI included in the display system of FIG. 1.

FIG. 8 is a block diagram illustrating an example of a display moduleaccording to an embodiment.

FIG. 9 is a block diagram illustrating a touch screen system to whichthe display system is applied according to an embodiment.

FIG. 10 is a flowchart illustrating a method for driving the DDIaccording to an embodiment.

FIG. 11 is a flowchart illustrating an example of the method of FIG. 10.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure will bedescribed in more detail with reference to the accompanying drawings.Throughout the drawings, like components are designated by likereference numerals, and overlapping descriptions thereof will beomitted.

FIG. 1 is a block diagram illustrating a display system according to anembodiment.

Referring to FIG. 1, the display system 10 may include a display module1000, a host processor 2000, and a non-volatile memory (NVM) 3000. In anembodiment, the display system 10 may further include an additionalstorage device, an input/output device, a power management device, acommunication module, a camera module, a sensor module, and the like.

In an embodiment, the display system 10 may be implemented with a devicecapable of using or supporting a mobile industry processor interface(MIPI), e.g., a mobile device such as a mobile phone, a PDA, a PMP, asmart phone, or a wearable device.

The host processor 2000 may control overall operation of the displaymodule 1000. For example, the host processor 2000 may be implementedwith a system on chip (SOC). The host processor 2000 may be anapplication processor (AP) provided in a mobile device.

The host processor 2000 may include a first interface IF1, and maydirectly communicate data with the display module 1000, i.e., a displaydriver integrated chip (or display driver integrated circuit, DDI) 100included in the display module 1000 through the first interface IF1. Inan embodiment, the first interface IF1 may correspond to a mobileindustry processor interface (MIPI), and accord with MIPI AllianceSpecification for Display Serial Interface and MIPI AllianceSpecification for D-PHY. However, using MIPI for the first interface IFIis merely illustrative, and the communication interface between the hostprocessor 2000 and the DDI 100 is not limited thereto. For example, thefirst interface IF1 may be a serial high-speed interface for supportinga high-quality image of n-high definition (nHD) or higher.

The host processor 2000 may output a data load command CMD and outputcompensated image data CID obtained by compensating for an image data.In an embodiment, the host processor 2000 may provide the DDI 100 withthe data load command CMD for reading (loading) compensation data CDATAfrom the NVM 3000 through the first interface IF1. The DDI 100 convertsa packet structure of the data load command CMD into a format suitablefor the NVM 3000 to interpret, and provides the data load command CMDhaving the converted format to the NVM 3000. That is, the host processor2000 may indirectly communicate with the NVM 3000 via the display module1000.

Also, the host processor 2000 may provide the image data or thecompensated image data CID to the DDI 100 through the first interfaceIF1. The DDI 100 may convert the image data or the compensated imagedata CID into a data signal or data voltage suitable for image displayand provide the data signal or data voltage to a display panel 200.

In an embodiment, the host processor 2000 may perform opticalcompensation and/or afterimage compensation on the image data, based onthe compensation data CDATA loaded from the NVM 3000. For example, thecompensation data CDATA may include data offset values for opticalcompensation or afterimage compensation, and the host processor 2000 maygenerate the compensated image data CID by applying the data offsetvalues to the image data. In an embodiment, the host processor 2000 mayinclude an image data compensator 2020 for performing luminancecompensation, gray scale compensation, degradation compensation, etc.for the image data. The image data compensator 2020 may be implementedwith a hardware or software compensation algorithm. The hardware orsoftware compensation algorithm may be implemented using techniquesalready known in the art. For example, the image data compensator 2020may be implemented with the existing compensation circuits orcompensation blocks, typically disposed in the DDI 100. Accordingly, thecompensation blocks disposed in the DDI 100 can be eliminated, and thesize and power consumption of the DDI 100 can be reduced.

The display module 1000 may include the DDI 100 and the display panel200.

The display panel 200 may include a plurality of pixels to display animage.

The DDI 100 may be coupled to the host processor 2000 through the firstinterface IF1, and be coupled to the NVM 3000 through a second interfaceIF2. The DDI 100 may include an interface packet converter 150 forconverting a packet structure of each of first data compatible with thefirst interface IF1 and second data compatible with the second interfaceIF2.

The first data may include the data load command CMD, the image data,and the like. The second data may include the compensation data CDATAloaded from the NVM 3000.

In an embodiment, the second interface IF2 may correspond to a low-speedserial interface for data communication of the NVM 3000 (for example, aflash memory). For example, the second interface IF2 may correspond to aserial peripheral interface (SPI). However, using SPI for the secondinterface IF2 is merely illustrative. In other embodiments, the secondinterface IF2 may be a synchronous/asynchronous serial interface such asI2C or UART.

Since the first interface IF1 and the second interface IF2 are differentfrom each other, packet structures of data streams transmitted throughthe first interface IF1 and the second interface IF2 are different fromeach other. Thus, the NVM 3000 cannot directly receive the data loadcommand output from the host processor 2000. Similarly, the compensationdata CDATA loaded from the NVM 3000 cannot be directly provided to thehost processor 2000.

Accordingly, the interface packet converter 150 may convert a packetstructure of data compatible with the first interface IF1 into a packetstructure of data compatible with the second interface IF2, or convert apacket structure of data compatible with the second interface IF2 into apacket structure of data compatible with the first interface IF1. Forexample, the interface packet converter 150 may interpret a packetstructure of data received through each interface and then rearrange thepacket structure in a format that accords with an interface throughwhich the packet structure is to be transmitted. As an example, theinterface packet converter 150 may perform packet structure conversion(rearrangement) between the MIPI and the SPI. The converted dataincludes a content substantially identical to that of the original data,but has a format (packet structure) different from that of the originaldata.

For example, the interface packet converter 150 may convert data definedby standards of the MIPI into serial data (packet) defined by standardsof the SPI in the unit of one byte, or convert serial data defined bystandards of the SPI into a packet defined by standards of the MIPI.

In an embodiment, the interface packet converter 150 may include a firstconverter for rearranging a packet structure of the first data receivedthrough the first interface IF1 in a format compatible with the secondinterface IF2 and a second converter for rearranging a packet structureof the second data received through the second interface IF2 in a formatcompatible with the first interface IF1. The bidirection communicationbetween the host processor 2000 and the NVM 3000 may be performed byinterface conversion driving (data stream rearrangement) of theinterface packet conversion 150. Accordingly, image data compensationdriving in the host processor 2000 can be performed.

The DDI 100 may further include a timing controller and a data driver.The timing controller may generate a data signal for image display, ascan control signal, and a data control signal by receiving image dataprocessed through the first interface IF1. The data driver may generatethe data voltage, based on the data signal and the data control signal.

In an embodiment, the DDI 100 may further include a scan driver forgenerating a scan signal in response to the scan control signal.However, including the scan driver in the DDI is merely illustrative. Inother embodiments, the scan driver may be directly disposed in thedisplay panel 200.

The NVM 3000 stores compensation data CDATA for image compensation. TheNVM 3000 may be a flash memory. However, the NVM 3000 is not limited toa flash memory, and in other embodiments, the NVM 3000 may beimplemented with an NVM capable of processing data of 50 Mbits or more.In an embodiment, the compensation data CDATA may include at least oneof offsets for optical compensation and offsets for afterimagecompensation. That is, a large-capacity NVM 3000 is to be necessarilyincluded in the display system 10 so as to perform precise image datacompensation including afterimage compensation, optical compensation,and the like.

The NVM 3000 may communicate with the DDI 100 through the secondinterface IF2.

As described above, the DDI 100 includes the interface packet converter150 for performing packet structure conversion between the interface ofthe host processor 2000 and the interface of the NVM 3000. Thus, thedata communication between the host processor 2000 and the NVM 3000 canbe performed without increasing the number of channels (or pins) in thedisplay system 10. Accordingly, an image data compensation operation canbe performed in the host processor 2000 instead of the DDI 100.

Thus, the image compensation blocks disposed in the DDI 100 can beremoved, and the size and power consumption of the DDI 100 can bereduced. Accordingly, the manufacturing cost of the DDI 100 can bereduced.

FIG. 2 is a diagram schematically illustrating an example of the DDIaccording to an embodiment.

Referring to FIG. 2, the DDI 100 may include a first interface IF1 120for supporting communication with the host processor 2000, a secondinterface IF2 140 for supporting communication with a flash memory 3001,and an interface packet converter 150 for performing packet structureconversion of each of first data DAT1 compatible with the firstinterface IF1 and second data DAT2 compatible with the second interfaceIF2.

In an embodiment, the first interface IF1 may be the MIPI. The firstinterface IF1 of the DDI 100 may include a slave PHY corresponding tothe host processor 2000. For example, the PHY configuration of the firstinterface IF1 of the DDI 100 may include one clock lane module and atleast one data lane module. Each of the lane modules of the PHYconfiguration communicates with a corresponding lane module in the hostprocessor 200 through channels Clkp, Clkn, D0 p to D3 p, and D0 n to D3n.

The DDI 100 may receive image data, a data load command, and the likefrom the host processor 2000 through the first interface IF1. Also, theDDI 100 may transmit compensation data converted by the interface packetconverter 150 to the host processor 2000.

The second interface IF2 may be the SPI. For example, the secondinterface IF2 may be a quad SPI. Accordingly, the second interface IF2communicates with the flash memory 3001 through a clock/chip selectorchannel SCLK/CS and four data input/output channels DQ[0] to DQ[3].

The DDI 100 may receive compensation data corresponding to the data loadcommand from the flash memory 3001 through the second interface IF2.Also, the DDI 100 may transmit the data load command converted by theinterface packet converter 150 to the flash memory 3001.

FIG. 3 is a block diagram illustrating an example of the interfacepacket converter included in the DDI of the display system of FIG. 1.

Referring to FIGS. 1 to 3, the interface packet converter 150 mayinclude a first converter 152 and a second converter 154.

The first converter 152 may rearrange a packet structure of first datareceived through the first interface IF1 in a format compatible with thesecond interface IF2. In an embodiment, the first data may be a dataload command CMD1 for loading compensation data CDATA1 stored in theflash memory 3001. For example, the data load command CMD1 may have adata stream corresponding to the MIPI. The first converter 152 mayrearrange the data load command CMD1 as a data stream corresponding tothe second interface IF2, i.e., the SPI. The content of the converteddata load command CMD2 may be substantially identical to that of thedata load command CMD1. The converted data load command CMD2 may beprovided to the flash memory 3001 through the second interface IF2.

The second converter 154 may rearrange a packet structure of second datareceived through the second interface IF2 in a format compatible withthe first interface IF1. In an embodiment, the second data may becompensation data CDATA1 stored in the flash memory 3001. Thecompensation data CDATA1 may have a data stream corresponding to theSPI. The second converter 154 may rearrange the compensation data CDATA1as a data stream corresponding to the first interface IF1, i.e., theMIPI. The content of the converted compensation data CDATA2 may besubstantially identical to that of the compensation data CDATA1.

As described above, the host system 2000 and the flash memory 3001 canperform communication for image compensation via the DDI 100 includingthe interface packet converter 150.

FIG. 4 is a block diagram illustrating an example of a configuration ofthe first interface included in the DDI according an embodiment.

Referring to FIG. 4, the configuration of the first interface 120includes a PHY configuration according to MIPI standards.

The PHY configuration according to the MIPI standards includes one clocklane module and at least one data lane module. Each of the lane modulesof the PHY configuration may communicates with a corresponding lanemodule at the opposite side of a lane interconnect through twointerconnect lines Dp and Dn.

An example of the configuration of one lane having all functions isillustrated in FIG. 4. Each lane may include a control-interface logicCIL and an input/output unit TX, RX, and CD. The input/output unit TX,RX, and CD may include a transmitter TX, a receiver RX, and a collisiondetector CD. The input/output unit TX, RX, and CD has a high-speed (HS)function related to differential signal input/output simultaneouslyusing the two interconnect lines Dp and Dn and a low-power (LP) functionrelated to single-ended transmission that is individually operated ineach of the interconnect lines Dp and Dn.

While high-speed signals have a low voltage swing of, for example, about200 mV, low-power signals may have a high voltage swing of, for example,about 1.2 V.

The HS function is mainly used for high-speed data transmission, and theLP function is mainly used for control. In some cases the HS functionand the LP function may be selectively used. Such input/output functionsare controlled by the control-interface logic CIL. The control-interfacelogic CIL performs interfacing with a protocol layer and determines aglobal operation of each lane module.

The HS function may include a differential transmitter HS-TX and adifferential receiver HS-RX. A lane module may include only one of thedifferential transmitter HS-TX and the differential receiver HS-RX, orinclude both of the differential transmitter HS-TX and the differentialreceiver HS-RX. However, the differential transmitter HS-TX and thedifferential receiver HS-RX included in the lane module cannot beenabled at the same time.

The LP function may include a single-ended transmitter LP-TX, asingle-ended receiver LP-RX, and a low-power collision detector LP-CD.When the lane module includes the differential transmitter HS-TX, thelane module necessarily includes the single-ended transmitter LP-TX.Similarly, when the lane module includes the differential receiverHS-RX, the lane module necessarily includes the single-ended receiverLP-RX. The low-power collision detector LP-CD is required to performonly a bidirectional operation. The low-power collision detector LP-CDmay be enabled to detect a collision only when the single-endedtransmitter LP-TX drives low-power states.

In an embodiment, the data load command output from the host processor2000 may be transmitted to the DDI 100 through both of the HS functionand the LP function. The image data or compensated image data outputfrom the host processor 2000 may be transmitted to the DDI 100 throughthe HS function. The converted compensation data output from the DDI 100may be transmitted to the host processor 2000 through the LP function.

FIGS. 5A to 5C are diagrams schematically illustrating examples of apacket structure according to the first interface of FIG. 4.

The first interface IF1 corresponds to the MIPI. FIG. 5A illustrates along packet format, FIG. 5B illustrates a short packet format, and FIG.5C illustrates a data identifier.

Referring to FIG. 5A, a long packet may include a packet header PH of 32bits, a data payload PL having a variable byte number, and a packetfooter of 16 bits. The packet header PH may include a data identifierDID of 8 bits, a word count WC of 16 bits, and an error-correcting codeECC of 8 bits. Each of data D0 to Dk shown in FIG. 5A is data of 8 bits,and the number of data D0 to Dk, i.e., the number of bytes included inthe data payload PL corresponds to the word count WC. The packet footerPF may include a checksum CS of 16 bits.

Referring to FIG. 5B, a short packet is configured with a packet headerPH. The packet header PH may include a data identifier DID of 8 bits,data D0 and D1 of 2 bytes, and an error-correcting code ECC of 8 bits. Acommand (e.g., a data load command) may be included at the position ofthe data D0 and D1 depending on a data type of the short packet. Theshort packet does not include the packet footer, and the length of theshort packet is to be 4 bytes.

Referring to FIG. 5C, a data identifier DID may include two bits B7 andB6 for identifying a virtual channel VC and 6 bits B5 to B0 foridentifying a data type DT.

The interface packet converter 150 may identify whether a receivedpacket includes a command and a kind of the command with reference todata types DT of the data identifiers DID included in the long packetand the short packet. For example, the interface packet converter 150may determine whether the data load command is included in data withreference to the data type DT, and interpret the data. The interfacepacket converter 150 may rearrange the data load command in a packetstructure having a format that accords with the SPI. The content of thedata load command is substantially identical to that of the converteddata load command.

FIG. 6 is a diagram schematically illustrating an example of a packetstructure of the second interface included in the DDI.

The second interface may be the SPI. Referring to FIG. 6, the packetstructure defined by standards of the second interface may have a serialdata format including an address ADD, data DAT, and a checksum CS.

For example, the compensation data loaded (read) from the flash memory3001 may have the packet structure of FIG. 6. The interface packetconverter 150 may interpret compensation data and rearrange thecompensation data in a packet structure defined by standards of theMIPI. The content of the compensation data is substantially identical tothat of the converted compensation data.

FIG. 7A is a diagram schematically illustrating an example of driving ofthe DDI included in the display system of FIG. 1.

FIG. 7A shows driving of the DDI 100 that provides the data load commandCMD1 received from the host processor to the flash memory 3001.

The input/output unit of the first interface 120 of the DDI 100 mayreceive a data load command CMD1 through the interconnect lines Dp andDn.

When the data load command CMD1 is transmitted through the HS function,the data load command CMD1 may be provided to the interface packetconverter 150 via a data interface logic. The data interface logicperforms interfacing with the protocol layer at a high speed in the DDI100. As an example, the data interface logic may determine the data loadcommand CMD1 as a command signal, and the data load command CMD1 may beprovided to the interface packet converter 150 and then to the secondinterface 140 which includes a predetermined deserializer, based on thedetermination.

When the data load command CMD1 is transmitted through the LP function,the data load command CMD1 may be provided to the interface packetconverter 150 via a control interface logic. The control interface logicperforms interfacing with the protocol layer in the DDI 100.

The interface packet converter 150 may rearrange the data load commandCMD1 in a packet structure that accords with standards of the SPI. Therearranged data stream may be parallelized by an SPI deserializer to betransmitted in the format of a data load command CMD2 converted throughthe quad SPI to the flash memory 3001.

That is, the data load command of the MIPI format is rearranged as thedata load command CMD2 converted in the SPI format via the DDI 100 to betransmitted to the flash memory 3001. Accordingly, a command of the hostprocessor may be transmitted to the flash memory 3001.

FIG. 7B is a diagram schematically illustrating another example of thedriving of the DDI included in the display system of FIG. 1.

FIG. 7B illustrates driving of the DDI 100 that provides thecompensation data CDATA1 received from the flash memory 3001 to the hostmemory.

The flash memory 3001 loads the compensation data CDATA1 in response tothe converted data load command CMD2. The second interface 140 of theDDI 100 may receive the compensation data CDATA1 through a plurality ofsignal channels DQ. In an embodiment, the compensation data CDATA1 maybe an offset or weighted value for optical compensation, afterimagecompensation, etc.

The compensation data CDATA1 may be serialized through the deserializerincluded in the second interface 140 before being provided to theinterface packet converter 150. The interface packet converter 150 mayrearrange the compensation data CDATA1 as a packet defined by standardsof the MIPI in the unit of one byte. The converted compensation dataCDATA2 may be provided to the input/output unit via the most efficientdata interface logic in terms of speed. For example, the compensationdata may be rearranged in a packet structure defined as an RGB 24interface that is one of internal interfaces of the DDI 100. A packetstructure corresponding to the RGB 24 interface may be compatible withthat corresponding to the MIPI. The compensation data CDATA2 convertedin the packet structure corresponding to the RGB 24 interface may betransmitted to the host processor through the interconnect lines Dp andDn via the data interface logic. Here, the converted compensation dataCDATA2 is transmitted through the LP function. However, transmitting theconverted compensation data CDATA2 through the LP function is merelyillustrative. In other embodiments, the converted compensation dataCDATA2 may be transmitted through the HS function.

That is, the compensation data in the SPI format is rearranged as theconverted compensation data CDATA2 in the MIPI format via the DDI 100 tobe loaded to the host processor.

FIG. 8 is a block diagram illustrating an example of a display moduleaccording to an embodiment.

Referring to FIGS. 1 and 8, the display module 1000 may include a DDI100 and a display panel 200.

In FIG. 8, components identical to those described with reference toFIGS. 1 to 7B are designated by like reference numerals, and furtherdescriptions will be omitted.

The DDI 100 may include a first interface 120, a second interface 140,an interface packet converter 150, and a timing controller 180. The DDI100 may further include a scan driver 160 and a data driver 170.However, in some embodiments, the scan driver 160 may be directlymounted in the display panel 200.

The first interface 120 may support communication with the hostprocessor 2000, such as using the MIPI. The second interface 140 maysupport communication with the flash memory 3001, such as using the SPI.The interface packet converter 150 may perform packet structureconversion on each of first data compatible with the first interface 120and second data compatible with the second interface 140.

The timing controller 180 may control driving of the scan driver 160 andthe data driver 170. The timing controller 180 may generate data signalRGB for image display, a scan control signal SCS, and a data controlsignal DCS by receiving compensated image data CID processed through thefirst interface 120. The timing controller 180 may provide the scancontrol signal SCS to the scan driver 160 and provide the data controlsignal DCS to the data driver 170. The data control signal DCS mayinclude a source start signal, a source output enable signal, a sourcesampling clock, and the like.

The scan driver 160 may generate a scan signal in response to the scancontrol signal SCS. The scan driver 160 may sequentially orsimultaneously supply the scan signal in units of pixel rows to thedisplay panel 200.

The data driver 170 may generate a data voltage in response to the datasignal RGB and the data control signal DCS. The data driver 170 mayprovide the data voltage to the display panel 200.

The display panel 200 may include a plurality of scan lines SL1 to SLn,a plurality of data lines DL1 to DLm, and a plurality of pixel Prespectively coupled to the scan lines SL1 to SLn and the data line DL1to DLm.

FIG. 9 is a block diagram illustrating a touch screen system to whichthe display system is applied according to an embodiment.

In FIG. 9, components identical to those described with reference toFIGS. 1 to 8 are designated by like reference numerals, and furtherdescriptions will be omitted.

Referring to FIG. 9, the display system 20 may include an applicationprocessor (AP) 2100, an image processor 2120, a display module 1100, anda flash memory 3001. The display module 1100 may include a DDI 100, adisplay panel 200, a touch screen controller 300, and a touch screen400.

The AP 2100 may receive a command or data input from a user and controlthe DDI 100 and the touch screen controller 300, based on the input dataor command. The AP 2100 may be implemented with a graphic card, a systemon chip (SOC), etc.

The AP 2100 may be included in the host processor of FIG. 1, and provideimage data of the display panel 200 to the DDI 100.

The image processor 2120 may process image data. The image processor2120 may generate the image data provided to the DDI 100 or performimage processing on the image data, based on a touch signal providedfrom the touch screen controller 300. In an embodiment, the imageprocessor 2120 may be provided in the AP 2100.

The DDI 100 may drive the display panel 200 under the control of the AP2100. The DDI 100 may mediate communication for image compensationdriving between the AP 2100 and the flash memory 3001.

The display panel 200 may display an image signal received from the DDI100.

The touch screen controller 300 may be coupled to the touch screen 400,to receive sensing data input from the touch screen 400 and transfer theinput sensing data to the AP 2100.

The touch screen 400 may overlap with the display panel 200. In anembodiment, the touch screen 400 may be integrally implemented with thedisplay panel 200.

In an embodiment, the DDI 100 and the touch screen controller 300 mayshare a plurality of functional blocks, and be implemented as onesemiconductor chip.

FIG. 10 is a flowchart illustrating a method for driving the DDIaccording to an embodiment. FIG. 11 is a flowchart illustrating anexample of the method of FIG. 10.

The methods of FIGS. 10 and 11 have been described in detail withreference to FIGS. 1 to 8, and therefore, further descriptions will beomitted.

Referring to FIGS. 10 and 11, the DDI may mediate communication forcompensation driving of image data between the host processor and theflash memory.

As shown in FIG. 10, the DDI may transmit a data load command receivedfrom the host processor to the flash memory. Specifically, the DDI mayreceive a data load command for image compensation, which is output fromthe host processor, through the first interface (S100), convert(rearrange) a packet structure of the data load command to be compatiblewith the second interface (S200), and then transmit the converted dataload command to an external NVM through the second interface (S300).

Accordingly, the host processor can issue a compensation data loadcommand to the flash memory by using the DDI to mediate thecommunication with the flash memory.

As shown in FIG. 11, the DDI may transmit compensation data receivedfrom the flash memory to the host processor. Specifically, the DDI mayreceive compensation data loaded from the NVM through the secondinterface (S400), convert a packet structure of the compensation data tobe compatible with the first interface (S500), and then transmit theconverted compensation data to the host processor through the firstinterface (S600).

Accordingly, the flash memory can response to the data load command ofthe host processor and transmit the compensation data to the hostprocess by using the DDI to mediate the communication with the hostprocessor. An image data compensation operation can be performed in thehost process itself through such data communication.

As described above, in the DDI and the display system including the sameaccording to the embodiment of the present disclosure, the DDI mediatesdata communication between the host processor and the flash memory, sothat the host processor can directly perform image data compensationincluding optical compensation, afterimage compensation, and the like.Thus, a considerable number of channels for communication between thehost processor and various types of functional units can be eliminated.Further, image compensation blocks including the existing compensationcircuit and the like, which are typically disposed in the DDI, are canbe removed from the DDI, so that the size and manufacturing cost of theDDI can be reduced. Furthermore, image compensation driving is performedin the host processor instead of the DDI, so that the total powerconsumption of the display system can be reduced.

The present disclosure can be applied to display systems and electronicdevices, which include display modules. For example, the presentdisclosure can be applied to mobile display electronic devices, wearabledevices, and the like.

According to the present disclosure, the DDI mediates data communicationbetween the host processor and the flash memory by rearranging aninterface packet structure. Thus, compensation blocks disposed in theDDI are eliminated, and the size and power consumption of the DDI can bereduced. In addition, the number and power consumption of interconnectchannels can be reduced in display signal processing, and signals forsupporting other protocols and interfaces can be communicated withoutadding interconnect lines.

Further, according to the example embodiments, the display systemincludes the DDI, so that the host processor can directly perform imagedata compensation including optical compensation, afterimagecompensation, and the like. Thus, image compensation blocks such as acompensation circuit, and/or a compensation circuit chip can be removedfrom the DDI, so that the size and manufacturing cost of the DDI can bereduced. Further, image compensation driving is performed in the hostprocessor instead of the DDI, so that the total power consumption of thedisplay system can be reduced.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present disclosure asset forth in the following claims.

What is claimed is:
 1. A display system comprising: a host processorconfigured to output a data load command and outputs compensated imagedata obtained by compensating for image data; a non-volatile memoryconfigured to store compensation data for image compensation; and adisplay module controlled by the host processor, wherein the displaymodule includes: a display panel including a plurality of pixels todisplay an image based on the compensated image data; and a displaydriver integrated chip (DDI) coupled to the host processor through afirst interface, the DDI being coupled to the non-volatile memorythrough a second interface, the DDI including an interface packetconverter configured to perform packet structure conversion on each offirst data compatible with the first interface and second datacompatible with the second interface.
 2. The display system of claim 1,wherein the interface packet converter includes: a first converterconfigured to rearrange a packet structure of the first data receivedthrough the first interface in a format compatible with the secondinterface; and a second converter configured to rearrange a packetstructure of the second data received through the second interface in aformat compatible with the first interface.
 3. The display system ofclaim 2, wherein the first data corresponds to the data load command forloading data stored in the non-volatile memory, and the second datacorresponds to the compensation data read from the non-volatile memorybased on the data load command.
 4. The display system of claim 2,wherein the first interface corresponds to a mobile industry processorinterface (MIPI), and the second interface corresponds to a serialperipheral interface (SPI).
 5. The display system of claim 1, whereinthe compensation data includes at least one of offsets for opticalcompensation and offsets for afterimage compensation.
 6. The displaysystem of claim 5, wherein the host processor performs image datacompensation on the image data, based on the compensation data, togenerate the compensated image data, and provides the compensated imagedata to the display module through the first interface.
 7. The displaysystem of claim 5, wherein the host processor includes an image datacompensator configured to perform at least one of optical compensationand afterimage compensation on the image data, based on the compensationdata.
 8. The display system of claim 1, wherein the host processorperforms communication with the non-volatile memory via DDI.
 9. Adisplay driver integrated chip (DDI) comprising: a first interfacecoupled to communication channels for communication with an externalhost processor; a second interface coupled to communication channels forcommunication with an external memory, the second interface beingdifferent from the first interface; an interface packet converterconfigured to perform packet structure conversion on each of first datacompatible with the first interface and second data compatible with thesecond interface; and a timing controller configured to generate a datasignal for image display, a scan control signal, and a data controlsignal by receiving image data processed through the first interface.10. The DDI of claim 9, wherein the interface packet converter includes:a first converter configured to rearrange a packet structure of thefirst data received through the first interface in a format compatiblewith the second interface; and a second converter configured torearrange a packet structure of the second data received through thesecond interface in a format compatible with the first interface. 11.The DDI of claim 10, wherein the first data corresponds to a data loadcommand for loading data stored in the memory, and the second datacorresponds to data read from the memory, based on the data loadcommand.
 12. The DDI of claim 10, wherein the first interfacecorresponds to a mobile industry processor interface (MIPI), and thesecond interface corresponds to a serial peripheral interface (SPI). 13.The DDI of claim 9, wherein the first interface conforms with MIPIAlliance Specification for Display Serial Interface and MIPI AllianceSpecification for D-PHY.
 14. The DDI of claim 13, wherein the secondinterface corresponds to a low-speed serial interface.
 15. The DDI ofclaim 9, wherein the interface packet converter mediates datatransmission between the first interface and the second interface. 16.The DDI of claim 9, further comprising: a data driver configured togenerate a data voltage in response to the data signal and the datacontrol signal.
 17. The DDI of claim 9, further comprising: a scandriver configured to generate a scan signal in response to the scancontrol signal.
 18. A method for driving a display driver integratedchip (DDI), the method comprising: receiving a data load command forimage compensation, which is output from a host processor, through afirst interface; converting a packet structure of the data load commandto be compatible with a second interface; and transmitting the converteddata load command to an external non-volatile memory (NVM) through thesecond interface.
 19. The method of claim 18, further comprising:receiving compensation data loaded from the NVM through the secondinterface; converting a packet structure of the compensation data to becompatible with the first interface; and transmitting the convertedcompensation data to the host processor through the first interface. 20.The method of claim 19, wherein the first interface corresponds to amobile industry processor interface (MIPI), and the second interfacecorresponds to a serial peripheral interface (SPI).